VLSI Circuit Detection Through Tangled Logic Structures

This work proposes a method of automatic very-large-scale integration (VLSI) circuit analysis. Groups with irregular structure have highly interconnected cells; groups have more internal than external connections. Detecting Tangled Logic Structures (TLS) with a linear ordering allows to identify the functional structure of the circuit and the gate-level VLSI circuit. High-level functional blocks in circuit description consist of gate-level cells groups, which are also highly interconnected. TLS-blocks are smaller, they represent a cell of high-level circuit, and are thus more suitable for further functional circuit analysis than a gate-level VLSI circuit.

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