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Выявление высокоуровневых иерархических структур сверхбольших интегральных схем…
ISSN 0236-3933. Вестник МГТУ им. Н.Э. Баумана. Сер. Приборостроение. 2016. № 4
17
Abstract
Keywords
This work proposes a method of automatic very-large-scale
integration (VLSI) circuit analysis. Groups with irregular struc-
ture have highly interconnected cells; groups have more internal
than external connections. Detecting Tangled Logic Structures
(TLS) with a linear ordering allows to identify the functional
structure of the circuit and the gate-level VLSI circuit. High-level
functional blocks in circuit description consist of gate-level cells
groups, which are also highly interconnected. TLS-blocks are
smaller, they represent a cell of high-level circuit, and are thus
more suitable for further functional circuit analysis than a gate-
level VLSI circuit
Very-large-scale integration (VLSI),
tangled logic structures (TLS),
functional circuit analysis
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