Application of Multidetector Phased-Locked Loop System for Reducing Hindrances of Divisibility in Frequency Synthesizers

The mathematical model is obtained for the multidetector system of pulse phaselocked loop with a fractional frequency divider that uses the delta-sigma modulation and with a set of phase-frequency detectors operating in parallel and in series with non-identical currents of charge pumping. The program for calculating a level of divisibility hindrance is developed on the basis of the obtained model. The calculation results showing the levels of divisibility hindrances depending on the number of the applied detectors are given for four cases of forming the currents of charge and discharge.